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SDRAM latency refers to delays in transmitting data between the CPU and SDRAM. SDRAM latency is often measured in memory bus clock cycles. However, the CPU operates faster than the memory, so it must wait while the proper segment of memory is located and read, before the data can be sent back. This also adds to the total SDRAM latency. ==SDRAM access== SDRAM is notationally organized into a grid like pattern, with "rows" and "columns". The data stored in SDRAM comes in blocks, defined by the coordinates of the row and column of the specific information. The steps for the memory controller to access data in SDRAM follow in order: # First, the SDRAM is in an idle state. # The controller issues the "active" command. It activates a certain row, as indicated by the address lines, in the SDRAM chip for accessing. This command typically takes a few clock cycles. # After the delay, column address and either "read" or "write" command is issued. Typically the read or write command can be repeated every clock cycle for different column addresses (or a burst mode read can be performed). The read data isn't however available until a few clock cycles later, because the memory is pipelined. # When an access is requested to another row, the current row has to be deactivated by issuing the "precharge" command. The precharge command takes a few clock cycles before a new "active" command can be issued. SDRAM access has four main measurements (quantified in FSB clock cycles) important in defining the SDRAM latency in a given computer (the 't' prefixes are for 'time'): ;tCAS :''tCAS'' is the number of clock cycles needed to access a certain column of data in SDRAM. CAS latency is the column address strobe time, sometimes referred to as tCL. ;tRCD (RAS to CAS delay) :''tRCD'' is the number of clock cycles delay required between an active command row address strobe (RAS) and a CAS. It is the time required between the memory controller asserting a row address, and then asserting a column address during the subsequent read or write command. tRCD stands for row address to column address delay time. ;tRP (row precharge) :''tRP'' is the number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. It stands for row precharge time. ;tRAS (row active time) :''tRAS'' is the minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. It's known as active to precharge delay. According to Mushkin.com, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out. (). It stands for row address strobe time. Pictorially the timings operate as follows: Initially, the row address is sent to the DRAM. After tRCD, the row is open and may be accessed. Because this is an SDRAM, multiple column access can be in progress at once. Each read takes time tCAS. When we are done accessing the column, we precharge the SDRAM, which returns us to the starting state after time tRP. Two other time limits that must also be maintained are tRAS, the time for the refresh of the row to complete before it may be closed again, and tWR, the time that must elapse after the last write before the row may be closed. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「SDRAM latency」の詳細全文を読む スポンサード リンク
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